Advanced Clock Drivers Devices

Freescale Semiconductor

7

MPC9850

Figure 4. MPC9850 AC Test Reference (LVDS Outputs)

Figure 5. MPC9850 AC Test Reference (LVCMOS Outputs)

1. AC characteristics are design targets and pending characterization.

2. AC characteristics apply for parallel output termination of 50

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

Input and Output Timing Specification

Input Reference Frequency (25 MHz input)

Input Reference Frequency (33 MHz input)

XTAL Input

3. In bypass mode, the MPC9850 divides the input reference clock.

25

33

25

250

MHz

MHz

MHz

MHz

PLL bypass

2000

MHz

Output Frequency

Bank A output

Bank B output

Bank C output

15.87

15.87

50

200

200

500

MHz

MHz

MHz

PLL locked

Reference Input Pulse Width

2

ns

Input Frequency Accuracy

100

ppm

Output Rise/Fall Time

150

500

ps

20% to 80%

DC

Output Duty Cycle

43

47

50

50

57

53

%

Bank A and B

Bank C

PLL Specifications

Maximum PLL Lock Time

10

ms

MR Hold Time on Power Up

10

ns

MR Hold Time

10

ns

Skew and Jitter Specifications

Output-to-Output Skew (within a bank)

50

ps

Output-to-Output Skew (across banks A and B)

400

ps

Cycle-to-Cycle Jitter

200

150

ps

ps

Bank A and B

Bank C

Period Jitter

200

ps

Bank A and C

I/O Phase Jitter

RMS (1

σ)

50

ps

Bank A and C

Pulse

Generator

Z = 50

Ω

DUT MPC9850

Pulse

Generator

Z = 50

Ω

DUT MPC9850