TLE8082ES datasheet(45/61 Pages) INFINEON

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Serial Peripheral Interface (SPI)

The device has a 16 bit Serial Peripheral Interface (SPI). The SPI is a full duplex synchronous serial interface with

3 inputs and 1 output.

CSN: Chip Select Not (low active) input

SCK: SPI Clock input

SI: Slave Input

SO: Slave Output

The data information at SI and SO is synchronous to the SPI clock. The output levels of the SPI pins are related

to pin V5VI.

CSN

SCK

SPI

Interface

and

Chip Control

V5VI

Enable

Figure 12

SPI Function diagram

9.1

Parallel SPI operation together with TLE8080ES

The implementation of the SPI and the definition of the registers (two addresses for CTRL register) enable a

parallel operation of the SPI communication together with the device TLE8080EM.

9.2

SPI mode definition

A communication frame starts with the falling edge at CSN. At the beginning the clock must be "0" according to

timing definition (Figure 16). The data at pin SI is sampled with the falling edge of SCK. The data at pin SO is

shifted with the rising edge of SCK. The communication frame ends with the rising edge at CSN. At that time the

data received via pin SI is executed and stored internally and the result of the request is prepared for the next

communication as output data. A correct communication frame consists of 16 bits and starts with the MSB first.

TLE8082ES

Small engine management IC

Serial Peripheral Interface (SPI)

Datasheet

Rev. 1.0

2021-03-23

TLE8082ES Datasheet(PDF) 45 Page - Infineon Technologies AG