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PIMXRT516SCVL2A Datasheet(PDF) 53 Page - NXP Semiconductors |
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PIMXRT516SCVL2A Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 124 page  Electrical characteristics i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021 NXP Semiconductors 53 4.4.4 SWD timing parameters Figure 13 depicts the SWD timing. Figure 13. SWD timing Table 42. JTAG timing parameters ID Parameter Value Unit Min Max J0 TCK frequency — 25 MHz J1 TCK cycle time 40 — ns J2 TCK pulse width 20 — ns J3 Input data setup time 5 — ns J4 Input data hold time 5 — ns J5 Output data valid time — 15.2 ns J6 Output high impedance time — 15.2 ns J7 TRST_B assert time 100 — ns J8 TRST_B setup time to TCK edge 18 — ns S1 S2 SWD_CLK (input) SWD_DIO SWD_DIO S3 S4 S5 S6 SWD_DIO S2 |
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