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AS6VA25616 Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation

No. de pieza AS6VA25616
Descripción Electrónicos  2.7V to 3.3V 256K x 16 Intelliwatt low-power CMOS SRAM with one chip enable
PDF  9 Pages
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Fabricante Electrónico  ALSC [Alliance Semiconductor Corporation]
Página de inicio  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS6VA25616 Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation

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ALLIANCE SEMICONDUCTOR
10/6/00
AS6VA25616
Functional description
The AS6VA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS)
permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6VA25616 is guaranteed not to exceed 66
µW power
consumption at 3.3V and 55 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins
I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is
active, or (UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written
and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the JEDEC
standard 400-mm, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Key: X = Don’t care, L = Low, H = High.
Parameter
Device
Symbol
Min
Max
Unit
Voltage on VCC relative to VSS
VtIN
–0.5
VCC + 0.5
V
Voltage on any I/O pin relative to GND
VtI/O
–0.5
V
Power dissipation
PD
–1.0
W
Storage temperature (plastic)
Tstg
–65
+150
oC
Temperature with VCC applied
Tbias
–55
+125
oC
DC output current (low)
IOUT
–20
mA
CS
WE
OE
LB
UB
Supply
Current
I/O1–I/O8
I/O9–I/O16
Mode
HX
XX
X
ISB
High Z
High Z
Standby (ISB)
LX
X
H
H
LH
H
X
X
ICC
High Z
High Z
Output disable (ICC)
LH
L
LH
ICC
DOUT
High Z
Read (ICC)
H
L
High Z
DOUT
LL
DOUT
DOUT
LL
X
LH
ICC
DIN
High Z
Write (ICC)
H
L
High Z
DIN
LL
DIN
DIN



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