Advanced CMOS TTL Input – 74ACT04

Rev 1.1

08/03/21

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

4.5V

4.4

4.4

4.4

5.5V

5.4

5.4

5.4

V

6. Maximum test duration 2ms, one output loaded at a time.

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5.0V

8.5

9

9

Maximum Propagation

Delay

Input A to Output Y

(Figure 1)

5.0V

Input

tr = tf =3.0ns

8

8.5

8.5

ns

TYPICAL

Maximum Input

Capacitance

5.0V

4.5

pF

Power Dissipation

Capacitance

5.0V

30

pF

4.5V

3.86

3.76

3.76

Minimum High-Level

Output Voltage

5

V

5.5V

4.86

4.76

4.76

Maximum Input

Leakage Current

5.5V

±0.1

±1.0

±1.0

µA

Additional Maximum

5.5V

0.6

1.5

1.5

mA

5.5V

-

75

75

Minimum Dynamic

Output Current

6

5.5V

-

-75

-75

mA

Maximum Quiescent

Supply Leakage

Current

5.5V

4

40

40

µA

7. Not production tested in die form, characterized by chip design and tested in package.

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