MC56F81663 datasheet(63/73 Pages) NXP

63 / 73 page

Table 35. SPI timing (continued)

Characteristic

Symbol

Min

Max

Unit

See Figure

Master

Slave

—

Figure 17

Figure 18

Figure 19

Enable lead time

Master

Slave

tELD

—

Figure 19

Enable lag time

Master

Slave

tELG

—

Figure 19

Clock (SCK) high time

Master

Slave

tCH

—

Figure 16

Figure 17

Figure 18

Figure 19

Clock (SCK) low time

Master

Slave

tCL

—

Figure 19

Data set-up time required for inputs

Master

Slave

tDS

—

Figure 16

Figure 17

Figure 18

Figure 19

Data hold time required for inputs

Master

Slave

tDH

—

Figure 16

Figure 17

Figure 18

Figure 19

Access time (time to data active

from high-impedance state)

Slave

—

Figure 19

Disable time (hold time to high-

impedance state)

Slave

—

Figure 19

Data valid for outputs

Master

Slave (after enable edge)

tDV

—

Figure 16

Figure 17

Figure 18

Figure 19

Data invalid

Master

Slave

tDI

—

Figure 16

Figure 17

Figure 18

Figure 19

Rise time

Figure 16

Table continues on the next page...

PWMs and timers

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 Datasheet(PDF) 63 Page - NXP Semiconductors

MC56F81663 Datasheet(HTML) 63 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Descarga

Enlace URL