STM32WLE4JC datasheet(29/145 Pages) STMICROELECTRONICS

29 / 145 page

DS13105 Rev 8

29/145

STM32WLE5/E4xx

Functional overview

HSI16, depending on the software configuration.

•

Standby mode: VCORE domain is powered off. However, it is possible to preserve the

SRAM2 content as detailed below:

–

Standby mode with SRAM2 retention when the RRS bit is set in the PWR control

regulator.

–

Standby mode when the RRS bit is cleared in the PWR control register 3

(PWR_CR3). In this case the main regulator and the low-power regulator are

powered off.

All clocks in the VCORE domain are stopped. PLL, MSI, HSI16 and HSE32 are disabled.

LSI and LSE can be kept running.

Th RTC can remain active (Standby mode with RTC, Standby mode without RTC). The

sub-GHz radio and the PVD may also remain active when enabled independent from

the CPU. In Standby mode, the PVD selects its lowest level.

The system clock, when exiting Standby modes, is MSI at 4 MHz.

•

Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are

stopped. PLL, MSI, HSI16, LSI and HSE32 are disabled. LSE can be kept running. The

system clock when exiting the Shutdown mode, is MSI at 4 MHz. In this mode, the

supply voltage monitoring is disabled and the product behavior is not guaranteed in

case of a power voltage drop.

The table below summarizes the peripheral features over all available modes. Wakeup

capability is detailed in gray cells.

Table 7. Functionalities depending on system operating mode(1)

Peripheral

Stop 0

Stop 1

Stop 2

Standby Shutdown

CPU

-R

Sub-GHz radio system

O-

Flash memory

(up to 256 Kbytes)

YO(2) O(3)

O(2)

(3)

-R

Flash memory interface

-R

SRAM1

O(2)

YO(2)

-R

SRAM2

O(2)

YO(2)

-R

-O(4)

Backup registers

-R

Brownout reset (BOR)

Y-

Programmable voltage

detector (PVD)

OO(5) O(5)

Peripheral voltage monitor

(PVM3)

O-

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