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STM32G474PBY3TR Datasheet(PDF) 219 Page - STMicroelectronics |
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STM32G474PBY3TR Datasheet(HTML) 219 Page - STMicroelectronics |
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219 / 236 page  DS12288 Rev 5 219/236 STM32G474xB STM32G474xC STM32G474xE Package information 232 TFBGA100 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 70. TFBGA100 - 8 x 8 mm, low-profile quad flat package top view example 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. Stencil opening 0.400 mm Stencil thickness Between 0.100 mm and 0.125 mm Pad trace width 0.120 mm Table 118. TFBGA100 - recommended PCB design rules (continued) Dimension Recommended values (1) Product identification STM32G474 VEH6 A YWW Pin 1 identification Revision code Date code MS51946V1 |
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