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STM32G474PBY3TR Datasheet(PDF) 192 Page - STMicroelectronics

No. de pieza STM32G474PBY3TR
Descripción Electrónicos  Arm® Cortex®-M4 32-bit MCUFPU, 170 MHz / 213 DMIPS, 128 KB SRAM, rich analog, math acc, 184 ps 12 chan Hi-res timer
PDF  236 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G474PBY3TR Datasheet(HTML) 192 Page - STMicroelectronics

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Electrical characteristics
STM32G474xB STM32G474xC STM32G474xE
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DS12288 Rev 5
Table 103. Synchronous multiplexed PSRAM write timings(1)(2)(3)
1. CL = 30 pF.
2. Guaranteed by characterization results.
3. Clock ratio R = (HCLK period /FMC_CLK period).
Symbol
Parameter
Min
Max
Unit
tw(CLK)
FMC_CLK period
R*THCLK - 0.5
-
ns
td(CLKL-NExL)
FMC_CLK low to FMC_NEx low (x=0..2)
-
1.5
td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
R*THCLK/2 + 1
-
td(CLKL-NADVL) FMC_CLK low to FMC_NADV low
-
2.5
td(CLKL-NADVH) FMC_CLK low to FMC_NADV high
3.5
-
td(CLKL-AV)
FMC_CLK low to FMC_Ax valid (x=16…25)
-
4
td(CLKH-AIV)
FMC_CLK high to FMC_Ax invalid (x=16…25)
R*THCLK/2 + 1
-
td(CLKL-NWEL) FMC_CLK low to FMC_NWE low
-
2
td(CLKH-NWEH) FMC_CLK high to FMC_NWE high
R*THCLK/2 + 1
-
td(CLKL-ADV)
FMC_CLK low to FMC_AD[15:0] valid
-
3
td(CLKL-ADIV)
FMC_CLK low to FMC_AD[15:0] invalid
0
-
td(CLKL-DATA)
FMC_A/D[15:0] valid data after FMC_CLK low
-
3
td(CLKL-NBLL)
FMC_CLK low to FMC_NBL low
1
-
td(CLKH-NBLH) FMC_CLK high to FMC_NBL high
R*THCLK/2 + 1.5
-
tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
1.5
-
th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high
4
-



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