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STM32G474PBY3TR Datasheet(PDF) 181 Page - STMicroelectronics |
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STM32G474PBY3TR Datasheet(HTML) 181 Page - STMicroelectronics |
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181 / 236 page  DS12288 Rev 5 181/236 STM32G474xB STM32G474xC STM32G474xE Electrical characteristics 200 5.3.28 FSMC characteristics Unless otherwise specified, the parameters given in Table 94 to Table 107 for the FMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 17, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 x VDD Refer to Section 5.3.14: I/O port characteristics for more details on the input/output characteristics. Asynchronous waveforms and timings Figure 40 through Figure 43 represent asynchronous waveforms and Table 94 through Table 101 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • AddressSetupTime = 0x1 • AddressHoldTime = 0x1 • DataHoldTime = 0x1 • ByteLaneSetup = 0x1 • DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) • BusTurnAroundDuration = 0x0 In all timing tables, the THCLK is the HCLK clock period. tv(TX) Data output valid time Master mode - 0.5 1.5 ns Slave mode - 10 22 th(RX) Data output hold time Master mode 0 - - Slave mode 7 - - 1. Based on characterization, not tested in production. Table 93. USART electrical characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit |
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