Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock frequency

-

400

kHz

Clock pulse width high

600

-

ns

Clock pulse width low

1300

-

ns

SDA (out) fall time

20 (2)

300

ns

Input signal rise time

(3)

(3)

ns

Input signal fall time

(3)

(3)

ns

100

-

ns

0

-

ns

Data out hold time

50

-

ns

Clock low to next data valid (access time)

-

900

ns

Start condition setup time

600

-

ns

600

-

ns

600

-

ns

Time between Stop condition and next Start condition

1300

-

ns

Write time

-

5

ms

-

Pulse width ignored (input filter on SCL and SDA) - single glitch

-

50

ns

1. Characterized only, not tested in production.

3. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C specification

4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of

SDA

M24128X-FCU

DC and AC parameters

DS12680 - Rev 2

page 21/35