LP8733 datasheet(39/85 Pages) TI

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SDA

START

Condition

SCL

STOP

Condition

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

SCL

SDA

LP8733-Q1

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SNVSB64 – SEPTEMBER 2018

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7.5 Programming

7.5.1 I2C-Compatible Interface

The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every device on

the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates

or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed on the line and

remain HIGH even when the bus is idle. The LP8733xx-Q1 supports standard mode (100 kHz), fast mode (400

kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).

7.5.1.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

Figure 23. Data Validity Diagram

7.5.1.2 Start and Stop Conditions

The LP8733xx-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the

beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while

SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C

master always generates the START and STOP conditions.

Figure 24. Start and Stop Sequences

The I2C bus is considered busy after a START condition and free after a STOP condition. During data

transmission the I2C master can generate repeated START conditions. A START and a repeated START

condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock

signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 25 shows the

SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.

LP8733 Datasheet(PDF) 39 Page - Texas Instruments

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