REV. 0

AD10226

–5–

PIN CONFIGURATION

35mm SQUARE

BOTTOM VIEW

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

24

22

20

18

16

14

12

10

8

6

4

2

25

23

21

19

17

15

13

11

9

7

5

3

1

PIN FUNCTION DESCRIPTIONS

Mnemonic

Function

AGNDA

A Channel Analog Ground. A and B grounds should be connected as close to the device as possible.

REF_A_OUT

A Channel Internal Voltage Reference

NC

No connection

Analog Input for A side ADC (– input)

Analog Input for A side ADC (+ input)

Analog Positive Supply Voltage (nominally 5.0 V)

DGNDA

A Channel Digital Ground

D11A–D0A

Digital Outputs for ADC A. D0 (LSB)

ENCODEA

Complement of ENCODE

ENCODEA

Data conversion initiated on the rising edge of ENCODE input.

Digital Positive Supply Voltage (nominally 3.3 V)

DGNDB

B Channel Digital Ground

D11B–D0B

Digital Outputs for ADC B. D0 (LSB)

AGNDB

B Channel Analog Ground. A and B grounds should be connected as close to the device as possible.

Digital Positive Supply Voltage (nominally 3.3 V)

ENCODEB

Complement of ENCODE

ENCODEB

Data conversion initiated on rising edge of ENCODE input.

REF_B_OUT

B Channel Internal Voltage Reference

Analog Input for B side ADC (– input)

Analog Input for B side ADC (+ input)

Analog Positive Supply Voltage (nominally 5.0 V)

DFS

Data format select. Low = Two’s Complement, High = Binary.

SFDR Mode

CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic

range (SFDR) performance. It is useful in applications where the dynamic range of the system is limited by discrete spurious

frequency content caused by nonlinearities in the ADC transfer function. SFDR Mode = 0 for normal operation.