August 2004

ASM5CVF857

rev 1.2

2.5V Wide-Range Frequency Clock Driver (60 MHz

– 200 MHz)

1 of 15

Notice: The information in this document is subject to change without notice.

2.5V Wide-Range Frequency Clock Driver (60MHz

– 200MHz)

Features

•

Low skew; low jitter PLL clock driver.

•

1 to 10 differential clock distribution (SSTL_2).

•

Feedback pins for input to output synchronization.

•

PDB for power management.

•

Spread spectrum tolerant inputs.

•

Auto-PD when input signal removed.

•

Choice of static phase offset for easy board tuning:

• -XXX = device pattern number for options listed

below:

• PCV857-025 - 0 ps

• PCV857-1300 - +50 ps

Product Description

levels.

ASM5CVF857 is a zero-delay buffer that

distributes a differential clock input pair (CLK_INT,

CLK_INC) to ten differential pairs of clock outputs

(CLKT[0:9],

CLKC[0:9])

and

one

differential

pair

feedback clock output (FB_OUT, FB_OUTC). The clock

outputs are controlled by the input clocks (CLK_INT,

CLKINC), the feedback clocks (FB_INT, FB_INC), the

2,5V LVCMOS input (PDB), and the analog power input

the receivers are disabled, the PLL is turned off, and

is grounded, the PLL is turned off and bypassed for test

purposes.

When the input frequency is less than the operating

frequency of the PLL, approximately 20MHz, the device

will enter a low power mode. An input frequency

detection circuit on the differential inputs, independent

from the input buffers, will detect the low frequency

condition and perform the same low power features as

and when the PDB input is low. When the input

frequency increases to greater than approximately

20MHz, the PLL will be turned back on, the inputs and

outputs will be enabled, and the PLL will obtain phase

lock

between

the

feedback

clock

pair (FB_INT,

FB_INC) and the input clock pair (CLK_INT, CLK_INC).

The PLL in the ASM5CVF857 clock driver uses the

input clocks (CLK_INT, CLKINC) and the feedback

clocks (FB_INT, FB_INC) to provide high-performance,

low-skew, low-jitter output differential clocks (CLKT[0:9],

CLKC[0:9]). ASM5CVF857 is also able to track spread

spectrum clock (SSC) for reduced EMI.

ASM5CVF857 is characterized for operation from 0°C

to 85°C.

Applications

•

DDR Memory Modules / Zero Delay Board Fan

Out.

•

Provides complete DDR DIMM logic solution with

ASM4SSTVF16857, ASM4SSTVF16859 &

ASM4SSTVF32852.

Specifications

•

Meets PC3200 specification for DDR-I 400 support.

•

Covers all DDRI speed grades.

Switching Characteristics

•

CYCLE-CYCLE jitter : <50ps.

•

OUT-OUTPUT skew: <40ps.

•

Period jitter: ±30ps.