May 2005

ASM2I99448

rev 0.3

3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

3 of 15

Notice: The information in this document is subject to change without notice.

Table 2. PIN CONFIGURATION

Pin#

Pin Name

I/O

Type

Function

4,3

PCLK, PCLK

Input

LVPECL

LVPECL Clock Inputs

2

CCLK

Input

LVCMOS

Alternative clock signal input

1

CLK_SEL

Input

LVCMOS

Clock input select

5

CLK_STOP

Input

LVCMOS

Clock output enable/disable

6

OE

Input

LVCMOS

Output enable/disable

(high–impedance tristate)

31,29,27,25,23,21,19,17,15,13,11,9

Q0 – Q11

Output

LVCMOS

Clock output

8,12,16,20,24,28,32

GND

Supply

Ground

Negative power supply (GND) for

I/O and core.

7,10,14,18,22,26,30

Supply

Positive power supply for I/O and

connected to the positive power

supply for correct operation

Table 3. ABSOLUTE MAXIMUM RATINGS

1

Symbol

Parameter

Min

Max

Unit

Supply Voltage

–0.3

3.9

V

DC Input Voltage

–0.3

V

DC Output Voltage

–0.3

V

DC Input Current

±20

mA

DC Output Current

±50

mA

Storage Temperature Range

–65

125

°C

Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect

device reliability.