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AS7C25512PFS32A Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C25512PFS32A Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 19 page  December 2004 Copyright © Alliance Semiconductor. All rights reserved. ® AS7C25512PFS32A AS7C25512PFS36A 12/23/04, v. 2.2 Alliance Semiconductor 1 of 19 2.5V 512K × 32/36 pipelined burst synchronous SRAM Features • Organization: 524,288 words × 32 or 36 bits • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/3.8 ns •Fast OE access time: 3.5/3.8 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package • Individual byte write and global write • Multiple chip enables for easy expansion • 2.5V core power supply • Linear or interleaved burst control • Snooze mode for reduced power-standby • Common data inputs and data outputs Logic block diagram Selection guide -166 -133 Units Minimum cycle time 6 7.5 ns Maximum clock frequency 166 133 MHz Maximum clock access time 3.5 3.8 ns Maximum operating current 290 270 mA Maximum standby current 85 75 mA Maximum CMOS standby current (DC) 40 40 mA Q0 Q1 512K × 32/36 Memory array Burst logic CLK CLR CE Address DQ CE CLK DQd CLK DQ Byte write registers register DQc CLK DQ Byte write registers DQb CLK DQ Byte write registers DQa CLK DQ Byte write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down DQ[a:d] 4 36/32 19 17 19 19 GWE BWE BWd ADV ADSC ADSP CLK CE0 CE1 CE2 BWc BWb BWa OE ZZ LBO OE CLK CLK 36/32 36/32 A[18:0] |
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