WM8742GEDSSLASHRV datasheet(46/66 Pages) CIRRUS

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WM8742

Rev 4.4

ADDRESS

BITS

NAME

DEFAULT

DESCRIPTION

DACLLSB

Attenuation

00h

[4:0]

LAT[4:0]

00 (0dB)

LSBs of attenuation data for left channel in 0.125dB steps. See Table

25 for details.

UPDATE

Attenuation data load control for left channel.

0 =

Store LAT[4:0] value but don’t update

1 = Store LAT[4:0] and update attenuation on registers 0-3

Table 53 R0 DACL LSB Attenuation Control Register

ADDRESS

BITS

NAME

DEFAULT

DESCRIPTION

DACLMSB

Attenuation

01h

[4:0]

LAT[9:5]

00 (0dB)

MSBs of attenuation data for left channel in 4dB steps. See Table 25

for details.

UPDATE

Attenuation data load control for left channel.

0 =

Store LAT[9:5] value but don’t update

1 = Store LAT[9:5] and update attenuation on registers 0-3

Table 54 R1 DACL MSB Attenuation Control Register

ADDRESS

BITS

NAME

DEFAULT

DESCRIPTION

DACRLSB

Attenuation

02h

[4:0]

RAT[4:0]

00 (0dB)

LSBs of attenuation data for right channel in 0.125dB steps. See

Table 25 for details.

UPDATE

Attenuation data load control for right channel.

0 =

Store RAT[4:0] value but don’t update

1 = Store RAT[4:0] and update attenuation on registers 0-3

Table 55 R2 DACR LSB Attenuation Control Register

ADDRESS

BITS

NAME

DEFAULT

DESCRIPTION

DACRMSB

Attenuation

03h

[4:0]

RAT[9:5]

00 (0dB)

MSBs of attenuation data for right channel in 4dB step. See Table 25

for details.

UPDATE

Attenuation data load control for right channel.

0 =

Store RAT[9:5] value but don’t update

1 = Store RAT[9:5] and update attenuation on registers 0-3

Table 56 R3 DACR MSB Attenuation Control Register

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