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LP6480 Datasheet(PDF) 9 Page - Lowpower Semiconductor inc |
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LP6480 Datasheet(HTML) 9 Page - Lowpower Semiconductor inc |
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9 / 10 page ![]() LP6480-01 Apr.-2017 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 9 of 10 Preliminary Datasheet LP6480 Thermal Calculations There are three types of losses associated with the LP6480 step-down converter: switching losses, conduction losses, and quiescent current losses. Conduction losses are associated with the RDS(ON) characteristics of the power output switching devices. Switching losses are dominated by the gate charge of the power output switching devices. At full load, assuming continuous conduction mode (CCM), a simplified form of the losses is given by: IQ is the step-down converter quiescent current. The term tsw is used to estimate the full load step-down converter switching losses. For the condition where the step-down converter is in dropout at 95% duty cycle, the total device dissipation reduces to: Since RDS(ON), quiescent current, and switching losses all vary with input voltage, the total losses should be investigated over the complete input voltage range. Given the total losses, the maximum junction temperature can be derived from the θJA for the SOP8 package which is 90℃/W. Layout Guidance When laying out the PC board, the following layout guideline should be followed to ensure proper operation of the LP6480: 1. The power traces, including the GND trace, the SW trace and the IN trace should be kept short, direct and wide to allow large current flow. The L connection to the SW pins should be as short as possible. Use several VIA pads when routing between layers. 2. The input capacitor (CIN) should connect as closely as possible to VIN (Pin 5) and GND to get good power filtering. 3. Keep the switching node, SW (Pins 6) away from the sensitive FB/OUT node. 4. The feedback trace or OUT pin should be separate from any power trace and connect as closely as possible to the load point. Sensing along a high-current load trace will degrade DC load regulation. 5. The output capacitor COUT and L should be connected as closely as possible. The connection of L to the SW pin should be as short as possible and there should not be any signal lines under the inductor. 6. The resistance of the trace from the load return to PGND should be kept to a minimum. This will help to minimize any error in DC regulation due to differences in the potential of the internal signal ground and the power ground. |
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