LP3992 datasheet(6/9 Pages) POWER

6 / 9 page

LP3992-05

May.-2017

Email: marketing@lowpowersemi.com

www.lowpowersemi.com

Page 6 of 9

Preliminary Datasheet

LP3992

Applications Information

Like any low-dropout regulator, the external capacitors

used with the LP3992 must be carefully selected for

regulator stability and performance. Using a capacitor

whose value is > 1µF on the LP3992 input and the

amount of capacitance can be increased without limit.

The input capacitor must be located a distance of not

more than 0.5 inch from the input pin of the IC and

returned to a clean analog ground. Any good quality

ceramic or tantalum can be used for this capacitor.

The capacitor with larger value and lower ESR

(equivalent series resistance) provides better PSRR

and line-transient response. The output capacitor must

meet both requirements for minimum amount of

capacitance and ESR in all LDOs application. The

LP3992 is designed specifically to work with low ESR

ceramic output capacitor in space-saving and

performance consideration. Using a ceramic capacitor

whose value is at least 1µF with ESR is > 25mΩ on the

LP3992 output ensures stability. The LP3992 still

works well with output capacitor of other types due to

the wide stable ESR range. Output capacitor of larger

capacitance can reduce noise and improve load

transient response, stability, and PSRR. The output

capacitor should be located not more than 0.5 inch

from the VOUT pin of the LP3992 and returned to a

clean analog ground.

Start-up Function Enable Function

The LP3992 features an LDO regulator enable/disable

function. To assure the LDO regulator will switch on,

the EN turn on control level must be greater than 1.4

volts. The LDO regulator will go into the shutdown

mode when the voltage on the EN pin falls below 0.4

volts. For to protecting the system, the LP3992 have a

quick-discharge function. If the enable function is not

needed in a specific application, it may be tied to VIN

to keep the LDO regulator in a continuously on state.

Thermal Considerations

Thermal protection limits power dissipation in LP3992.

When the operation junction temperature exceeds

150°C, the OTP circuit starts the thermal shutdown

function turn the pass element off. The pass element

turns on again after the junction temperature cools by

25°C. For continue operation, do not exceed absolute

maximum operation junction temperature 125°C.

The power dissipation definition in device is:

PD = (VIN−VOUT) x IOUT + VIN x IQ

The maximum power dissipation depends on the

thermal resistance of IC package, PCB layout, the rate

of surroundings airflow and temperature difference

between junction to ambient.

The maximum power dissipation can be calculated by

following formula:

PD(MAX) = ( TJ(MAX) − TA ) /θJA

Where TJ(MAX) is the maximum operation junction

temperature 125°C, TA is the ambient temperature

and the θJA is the junction to ambient thermal

resistance. For recommended operating conditions

specification of LP3992, where TJ(MAX) is the

maximum junction temperature of the die (125°C) and

TA is the maximum ambient temperature. The junction

to ambient thermal resistance (θJA is layout

dependent) for SOT23-5 package is 195°C/W.

PD(MAX) = (125°C−25°C) / 195 = 500mW

The maximum power dissipation depends on

operating ambient temperature for fixed TJ(MAX) and

thermal resistance θJA.

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