VSC7511 datasheet(49/324 Pages) MICROSEMI

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Functional Descriptions

VMDS-10488 VSC7511 Datasheet Revision 4.2

The output buffer provides the following additional options to configure its behavior.

•

Idle mode: Enabling idle mode (SERDES6G_OB_CFG.OB_IDLE) results in a remaining voltage of

less than 30 mV at the buffers differential outputs.

•

Slew Rate: Slew rate can be controlled by two configuration settings.

SERDES6G_OB_CFG.OB_SR_H provides coarse adjustments, and SERDES6G_OB_CFG.OB_SR

provides fine adjustments.

•

Skew control: In 1 Gbps SGMII mode, skew adjustment is controlled by

SERDES6G_OB_CFG1.OB_ENA_CAS. Skew control is not applicable to other modes.

3.4.8

SERDES6G Clock and Data Recovery (CDR) in 100BASE-FX

To enable clock and data recovery when operating SERDES6G in 100BASE-FX mode, set the following

•

SERDES1G_MISC_CFG.DES_100FX_CPMD_ENA = 1

•

SERDES1G_IBJ_CFG.IB_FX100_ENA = 1

•

SERDES1G_DES_CFG.DES_CPMD_SEL = 2

3.4.9

Energy Efficient Ethernet

The SERDES6G block supports Energy Efficient Ethernet as defined in IEEE Draft P802.3az. To enable

the low power modes, SERDES6G_MISC_CFG.TX_LPI_MODE_ENA and

SERDES6G_MISC_CFG.RX_LPI_MODE_ENA must be set. At this point, the attached PCS takes full

control over the high-speed output and input buffer activity.

3.4.10

SERDES6G Data Inversion

The data streams in the transmit and the receive direction can be inverted using

SERDES6G_MISC_CFG.TX_DATA_INV_ENA and SERDES6G_MISC_CFG.RX_DATA_INV_ENA. This

effectively allows for swapping the P and N lines of the high-speed serial link.

3.4.11

SERDES6G Signal Detection Enhancements

Signal detect information from the SERDES6G macro is normally directly passed to the attached PCS. It

is possible to enable a hysteresis such that the signal detect condition must be active or inactive for a

certain time before it is signaled to the attached PCS.

The signal detect assertion time (the time signal detect must be active before the information is passed to

a PCS) is programmable in SERDES6G_DIG_CFG.SIGDET_AST. The signal detect de-assertion time

(the time signal detect must be inactive before the information is passed to a PCS) is programmable in

SERDES6G_DIG_CFG.SIGDET_DST.

3.4.12

High-Speed I/O Configuration Bus

The high-speed SerDes macros are configured using the high-speed I/O configuration bus (MCB), which

is a serial bus connecting the configuration register set with all the SerDes macros. The

HSIO::MCB_SERDES1G_ADDR_CFG register is used for SERDES1G macros and

HSIO::MCB_SERDES6G_ADDR_CFG register is used for SERDES6G macros. The configuration

busses are used for both writing to and reading from the macros.

The SERDES6G macros are programmed as follows:

•

Program the configuration registers for the SERDES6G macro. For more information about

configuration options, see SERDES6G, page 29.

•

Transfer the configuration from the configuration registers to one or more SerDes macros by writing

the address of the macro (MCB_SERDES6G_ADDR_CFG.SERDES6G_ADDR) and initiating the

write access (MCB_SERDES6G_ADDR_CFG.SERDES6G_WR_ONE_SHOT).

OB_POL

Non-inverting mode.

Inverting mode.

Table 20 •

De-Emphasis and Amplitude Configuration (continued)

Configuration

Value

Description

VSC7511 Datasheet(PDF) 49 Page - Microsemi Corporation

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