EM78P153E

OTP ROM

This specification is subject to change without prior notice.

2002/03/01

13

1: enable TCIF interrupt

• Bit 1 (ICIE) ICIF interrupt enable bit.

0: disable ICIF interrupt

1: enable ICIF interrupt

• Bit 2 (EXIE) EXIF interrupt enable bit.

0: disable EXIF interrupt

1: enable EXIF interrupt

• Bits 3~7 Not used.

• Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".

• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig.

9.

• IOCF register is both readable and writable.

4.3 TCC/WDT & Prescaler

There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for either

the TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the

prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the

instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode,

are cleared by the “WDTC” or “SLEP” instructions. Fig. 5 depicts the circuit diagram of TCC/WDT.

• R1(TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input

(edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at

every instruction cycle (without prescaler). Referring to Fig. 5, CLK=Fosc/2 or CLK=Fosc/4, depends

on the CODE Option bit CLK. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is used if CLK bit

is "1". If TCC signal source is from external clock input, TCC is increased by 1 at every falling edge or

rising edge of TCC pin.

• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the

oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a

WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any

time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without

prescaler, the WDT time-out period is approximately 18 ms

Vdd = 3V, set up time period = 18ms ± 5%