TLE8110ED datasheet(70/74 Pages) INFINEON

70 / 74 page

Data Sheet

Rev. 1.0

2018-03-07

TLE8110ED

Smart Multichannel Low Side Switch with Parallel Control and SPI Interface

Control of the device

12.3.5

PMx - Parallel Mode Register CHx

The Parallel Mode Register PMx[1] allows to “inform” the device about externally parallel connected output

channels. If a PMx bit is set, the “lower” related Input Channel controls the indicated Output Channels to

achieve best possible matching and according to that highest efficiency of both channels. Additionally to that,

the CLAMPsafe feature allows high matching during clamping.

PMx Command

Parallel Mode Register CHx; Reset Value: 0000 0000 0000B= 000H

76543210

0000

PM910

PM89

PM78

PM56

PM34

PM23

PM12

Field

Bits

Type

Description

PMx

[11:8]

R/W

PMx

[7:0]

R/W

PMx - Parallel Mode Bit

0Direct Mode,

Parallel Mode of Channel 1 with x+1.

Default PMx[0] = 0.

Controlling Parallel Mode is possible between Channel 1 to 4, 5 to

6, 7 to 10. In between the groups, no parallel mode is supported but

possible.

In case Parallel Mode is chosen and a diagnosis error at only one of

the channels is detected, the according diagnosis bit is set. This

information mismatch can be caused by tolerance related

inbalance of the channels connected together in parallel mode.

The diagnosis bits should be or-operated by the Micro Controller

side.

TLE8110ED Datasheet(PDF) 70 Page - Infineon Technologies AG

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