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TMUX1237DCKR Datasheet(PDF) 21 Page - Texas Instruments |
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TMUX1237DCKR Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 31 page ![]() 21 TMUX1237 www.ti.com SCDS424A – DECEMBER 2019 – REVISED MARCH 2020 Product Folder Links: TMUX1237 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated 9.2.1.2 Detailed Design Procedure The application shown in Figure 17 demonstrates how to toggle between the DAC output and GND for control of a power amplifier using a single control input. The DAC output is utilized to bias the gate of the power amplifier and can be disconnected from the circuit using the select pin of the switch. The TMUX1237 helps eliminate overshoot in a system caused by switching between two different voltage levels on the source (Sx) input pins. Fast switching times create a step response on the output of switches or multiplexers which can cause system level overshoot and ringing depending on many factors such as load capacitance and board parasitics. The TMUX1237 improves system reliability by eliminating overshoot while still maintaining fast transition timing. The TMUX1237 can support 1.8-V logic signals on the control input, allowing the device to interface with low logic controls of an FPGA or MCU. The TMUX1237 can be operated without any external components except for the supply decoupling capacitors. The select pin is recommended to have a pull-down or pull-up resistor to ensure the input is in a known state if the control signal becomes disconnected. All inputs to the switch must fall within the recommend operating conditions of the TMUX1237 including signal range and continuous current. For this design with a supply of 5 V the signal range can be 0 V to 5 V and the max continuous current can be 50 mA. 9.2.1.3 Application Curve The TMUX1237 improves system reliability by eliminating overshoot while still maintaining fast transition timing. Figure 18 shows no overshoot on the TMUX1237 Drain - Output when switching between GND and a 3.3 V input on the source pins. The logic voltage (SEL) toggles from GND to a 1.8 V logic input signal which cause the drain pin (D) to switch from GND to 3.3 V. No overshoot is observed on the output and the system level transition timing is 86 ns. VDD = 5 V S1 = 0 V S2 = 3.3 V SEL = 0 V to 1.8 V Figure 18. No Overshoot When Switching Between Inputs |
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