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AS5047U-HTST Datasheet(PDF) 17 Page - ams AG |
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AS5047U-HTST Datasheet(HTML) 17 Page - ams AG |
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17 / 51 page ![]() ams Datasheet Page 17 [v1-00] 2018-Oct-30 Document Feedback AS5047U − Detailed Description Figure 19: SPI Timing Note(s): 1. Synchronization with the internal clock → 2 * t CLK_SYS + 10ns (e.g. at 9 MHz → 232ns) Parameter Description Min Max Units tL Time between CSn falling edge and CLK rising edge 350(1) ns tclk Serial clock period 100 ns tclkL Low period of serial clock 50 ns tclkH High period of serial clock 50 ns tH Time between last falling edge of CLK and rising edge of CSn tclk/2 ns tCSn High time of SS/ between two transmissions 350(1) ns tMOSI Data input valid to clock edge 20 ns tMISO CLK edge to data output valid 51 ns tOZ Time between CSn rising edge and MISO HiZ 10 ns |
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