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AM652X Datasheet(PDF) 62 Page - Texas Instruments |
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AM652X Datasheet(HTML) 62 Page - Texas Instruments |
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62 / 277 page  62 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Terminal Configuration and Functions Copyright © 2017–2019, Texas Instruments Incorporated 4.3.4 DDRSS 4.3.4.1 MAIN Domain Table 4-8. DDRSS0 Signal Descriptions SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] DDR_AC0 DDRSS Address and Command Bus IO A10 DDR_AC1 DDRSS Address and Command Bus IO D9 DDR_AC2 DDRSS Address and Command Bus IO C9 DDR_AC3 DDRSS Address and Command Bus IO E9 DDR_AC4 DDRSS Address and Command Bus IO A9 DDR_AC5 DDRSS Address and Command Bus IO E8 DDR_AC6 DDRSS Address and Command Bus IO F8 DDR_AC7 DDRSS Address and Command Bus IO C7 DDR_AC8 DDRSS Address and Command Bus IO C8 DDR_AC9 DDRSS Address and Command Bus IO D7 DDR_AC10 DDRSS Address and Command Bus IO E7 DDR_AC11 DDRSS Address and Command Bus IO A6 DDR_AC12 DDRSS Address and Command Bus IO F7 DDR_AC13 DDRSS Address and Command Bus IO D6 DDR_AC14 DDRSS Address and Command Bus IO C6 DDR_AC15 DDRSS Address and Command Bus IO F6 DDR_AC16 DDRSS Address and Command Bus IO E6 DDR_AC17 DDRSS Address and Command Bus IO E5 DDR_AC18 DDRSS Address and Command Bus IO D8 DDR_AC19 DDRSS Address and Command Bus IO D10 DDR_AC20 DDRSS Address and Command Bus IO E10 DDR_AC21 DDRSS Address and Command Bus IO C10 DDR_AC22 DDRSS Address and Command Bus IO F11 DDR_AC23 DDRSS Address and Command Bus IO B10 DDR_AC24 DDRSS Address and Command Bus IO D11 DDR_AC25 DDRSS Address and Command Bus IO B11 DDR_AC26 DDRSS Address and Command Bus IO C11 DDR_AC27 DDRSS Address and Command Bus IO E11 DDR_AC28 DDRSS Address and Command Bus IO E12 DDR_AC29 DDRSS Address and Command Bus IO D12 DDR_ALERTn DDRSS Parity Error IO D5 DDR_CK0N DDRSS Differential Clock (negative) IO B8 DDR_CK0P DDRSS Differential Clock (positive) IO A8 DDR_CK1N DDRSS Differential Clock (negative) IO B7 DDR_CK1P DDRSS Differential Clock (positive) IO A7 DDR_DM0 DDRSS Data Mask IO E1 DDR_DM1 DDRSS Data Mask IO C5 DDR_DM2 DDRSS Data Mask IO D14 DDR_DM3 DDRSS Data Mask IO B17 DDR_DQ0 DDRSS Data IO A3 DDR_DQ1 DDRSS Data IO B2 DDR_DQ2 DDRSS Data IO C2 DDR_DQ3 DDRSS Data IO D2 |
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