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AM652X Datasheet(PDF) 238 Page - Texas Instruments |
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AM652X Datasheet(HTML) 238 Page - Texas Instruments |
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238 / 277 page ![]() 3 2 Start Bit Data Bits UART _TXD i 5 Data Bits Bit Start 4 UART _RXD i 238 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated (1) U = UART baud time = 1/Programmed baud rate Figure 5-122. UART Timing For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in the device TRM. 5.9.5.24 USB The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the specification for timing details. The USB 3.1 GEN1 Dual-Role Device Subsystem is compliant with the Universal Serial Bus (USB) 3.1 Specification, revision 1.0. Refer to the specification for timing details. For more details about features and additional description information on the device Universal Serial Bus Subsystem (USB), see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. For more information, see section Universal Serial Bus (USB) Subsystem in the device TRM. 5.9.6 Emulation and Debug 5.9.6.1 Debug Trace Table 5-120 and Figure 5-123 assume testing over the recommended operating conditions and electrical characteristic conditions. Table 5-120. Debug Trace Switching Characteristics NO. PARAMETER DESCRIPTION MIN MAX UNIT DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 10.16 ns DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 4.33 ns DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 4.33 ns DBTR4 tosu(TRC_DATAV- TRC_CLK) Output setup time, TRC_DATA valid to TRC_CLK edge 1.27 ns DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.27 ns DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.27 ns DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.27 ns DBTR8 trx(TRC_CLK_DATA_CTL) Output rise time, 30% VDD to 70% VDD 0.75 ns DBTR9 tfx(TRC_CLK_DATA_CTL) Output fall time, 70% VDD to 30% VDD 0.75 ns |
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