| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AM652X Datasheet(PDF) 165 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM652X Datasheet(HTML) 165 Page - Texas Instruments |
|
165 / 277 page ![]() DDR_CK[1:0]P 1 DDR_CK[1:0]N 165 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated For more information, see section Gigabit Ethernet MAC (MCU_CPSW0) in the device TRM. 5.9.5.3 CSI2 NOTE For more information, see section Camera Adapter Layer (CAL) Subsystem in the device TRM. The camera adaptation layer (CAL) is a very flexible subsystem that enables connection to multiple cameras supporting MIPI CSI-2 over D-PHY serial interface, a LVDS serial interface, and a traditional parallel interface. The device includes one instantiation of CAL Subsystem named CALSS0, with a single companion CAMERARX0 instance. • CSI2 Port is compliant with MIPI CSI-2 protocol with four data lanes. 5.9.5.4 DDRSS For more details about features and additional description information on the device DDR3L, DDR4, and LPDDR4 Memory Interfaces, see the corresponding sections within Section 4.3, Signal Descriptions and Section 6, Detailed Description. The device has dedicated interfaces to DDR3L, DDR4, and LPDDR4 SDRAM. It supports JEDEC JESD79-3-1, JESD79-4B, and JESD209-4B standards compliant DDR3L, DDR4, and LPDDR4 SDRAM devices with the following features: • 16-bit or 32-bit data path to external SDRAM memory • Memory device capacity: Up to 32 GB address space available over one chip select Table 5-41 and Figure 5-34 present switching characteristics for DDRSS. Table 5-41. Switching Characteristics for DDRSS NO. PARAMETER DDR TYPE MODE MIN MAX UNIT 1 tc(DDR_CKP/D DR_CKN) Cycle time, DDR_CKP and DDR_CKN DDR3L 1.25 3.3 ns DDR4 1.25 1.6 LPDDR4 DDR PHY PLL: DDRPHY_PLLCR0[31] = 0 1.5 3.003 Figure 5-34. DDRSS Memory Interface Clock Timing For more information, see section DDR Subsystem (DDRSS) in the device TRM. |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |