BQ28Z610-R1 datasheet(11/32 Pages) TI1

11 / 32 page

BQ28Z610-R1

www.ti.com

SLUSE07 – JANUARY 2020

Product Folder Links: BQ28Z610-R1

Submit Documentation Feedback

7.25 N-CH FET Drive (CHG, DSG)

Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

Output voltage ratio

RatioDSG = (VDSG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10

MΩ between PACK and DSG

2.133

2.333

2.467

—

RatioCHG = (VCHG – VVC2)/VVC2, 2.2 V < VVC2 < 4.07 V, 10

MΩ between BAT and CHG

2.133

2.333

2.467

V(FETON)

Output voltage,

CHG and DSG on

VDSG(ON) = VDSG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ

between PACK and DSG

8.75

9.5

10.25

VCHG(ON) = VCHG – VVC2, 4.07 V ≤ VVC2 ≤ 18 V, 10 MΩ

between VC2 and CHG

8.75

9.5

10.25

V(FETOFF)

Output voltage,

CHG and DSG off

VDSG(OFF) = VDSG – VPACK, 10 MΩ between PACK and

DSG

–0.4

0.4

VCHG(OFF) = VCHG – VBAT, 10 MΩ between VC2 and CHG

–0.4

0.4

Rise time

VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2 V, CL =

4.7 nF between DSG and PACK, 5.1 kΩ between DSG

and CL, 10 MΩ between PACK and DSG

200

500

µs

VCHG from 0% to 35% VCHG(ON)(TYP), VVC2 ≥ 2.2 V, CL =

4.7 nF between CHG and VC2, 5.1 kΩ between CHG and

CL, 10 MΩ between VC2 and CHG

200

500

Fall time

VDSG from VDSG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF

between DSG and PACK, 5.1 kΩ between DSG and CL,

10 MΩ between PACK and DSG

300

µs

VCHG from VCHG(ON)(TYP) to 1 V, VVC2 ≥ 2.2 V, CL = 4.7 nF

between CHG and VC2, 5.1 kΩ between CHG and CL, 10

MΩ between VC2 and CHG

200

7.26 I

2C Interface I/O

Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VIH

Input voltage high

SCL, SDA, VREG = 1.8 V (STANDARD and FAST modes) 0.7 × VREG

VIL

Input voltage low

SCL, SDA, VREG = 1.8 V (STANDARD and FAST modes)

–0.5

0.3 × VREG

VOL

Output low voltage

SCL, SDA, VREG = 1.8 V, IOL = 1 mA (FAST mode)

0.2 × VREG

SCL, SDA, VREG > 2.0 V, IOL = 1 mA (STANDARD and

FAST modes)

0.4

CIN

Input capacitance

ILKG

Input leakage

current

µA

RPD

Pull-down resistance

3.3

kΩ

7.27 I

2C Interface Timing

Typical values stated where TA = 25ºC and VCC = 7.2 V, Min/Max values stated where TA = –40ºC to 85ºC and VCC = 2.2 V

to 7.6 V (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

NOM

MAX

UNIT

Clock rise time

10% to 90%

300

Clock fall time

90% to 10%

300

tHIGH

Clock high period

600

tLOW

Clock low period

1.3

µs

tSU(START)

Repeated start setup

time

600

td(START)

Start for first falling

edge to SCL

600

tSU(DATA)

Data setup time

100

BQ28Z610-R1 Datasheet(PDF) 11 Page - Texas Instruments

BQ28Z610-R1 Datasheet(HTML) 11 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Descarga

Enlace URL