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CS42432-DMZ Datasheet(PDF) 41 Page - Cirrus Logic

No. de pieza CS42432-DMZ
Descripción Electrónicos  108 dB, 192 kHz 4-in, 6-out TDM CODEC
PDF  62 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42432-DMZ Datasheet(HTML) 41 Page - Cirrus Logic

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DS673PP2
41
7.3
POWER CONTROL (ADDRESS 02H)
7.3.1
POWER DOWN ADC PAIRS(PDN_ADCX)
Default = 0
0 - Disable
1 - Enable
Function:
When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; and ADC2 - AIN3/AIN4) will re-
main in a reset state.
7.3.2
POWER DOWN DAC PAIRS (PDN_DACX)
Default = 0
0 - Disable
1 - Enable
Function:
When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4;
and DAC3 - AOUT5/AOUT6) will remain in a reset state. It is advised that any change of these bits
be made while the DACs are muted or the power down bit (PDN) is enabled to eliminate the possibility
of audible artifacts.
7.3.3
POWER DOWN (PDN)
Default = 0
0 - Disable
1 - Enable
Function:
The entire device will enter a low-power state when this function is enabled. The contents of the con-
trol registers are retained in this mode.
7
654
32
10
Reserved
PDN_ADC2
PDN_ADC1
Reserved
PDN_DAC3
PDN_DAC2
PDN_DAC1
PDN



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