CS5550

20

DS630F1

5. REGISTER DESCRIPTION

1. “Default**” => bit status after power-on or reset

2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.

5.1 Configuration Register

Address: 0

Default** = 0x000001

gain

Sets the gain of the AIN1 PGA

0 = gain is 10

1 = gain is 50

[IMODE IINV] Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.

00 = active low level (default)

01 = active high level

10 = falling edge (INT is normally high)

11 = rising edge (INT is normally low)

1HPF

Control the use of the High Pass Filter on AIN1 Channel.

0 = HPF disabled

1 = HPF enabled

2HPF

Control the use of the High Pass Filter on AIN2 Channel.

0 = HPF disabled

1 = HPF enabled

iCPU

Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals

are sampled, the logic driven by CPUCLK should not be active during the sample edge.

0 = normal operation (default)

1 = minimize noise when CPUCLK is driving rising edge logic

K[3:0]

Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal

clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-

tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero).

23

22

21

20

19

18

17

16

gain

15

14

13

12

11

10

9

8

IMODE

IINV

7

654

32

10

2HPF

1HPF

iCPU

K3

K2

K1

K0