WM8771FV datasheet(19/44 Pages) WOLFSON

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WM8771

PP Rev 2.0 December 2001

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8771 on the rising edge of BCLK

preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the

falling edge of BCLK preceding an ADCLRC transition and may be sampled on the rising edge of

BCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples

(Figure 12).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DIN1/2/3/4/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 12 Right Justified Mode TIming Diagram

I2S MODE

In I2S mode, the MSB of DIN1/2/3/4 is sampled by the WM8771 on the second rising edge of BCLK

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of

BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DIN1/2/3/4/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 13 I2S Mode TIming Diagram

WM8771FV Datasheet(PDF) 19 Page - Wolfson Microelectronics plc

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