LFEC datasheet(49/117 Pages) LATTICE

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3-13

DC and Switching Characteristics

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Derating Timing Tables

Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst-case

numbers in the operating range. Actual delays at nominal temperature and voltage for best-case process, can be

much better than the values given in the tables. To calculate logic timing numbers at a particular temperature and

voltage multiply the noted numbers with the derating factors provided below.

The junction temperature for the FPGA depends on the power dissipation by the device, the package thermal char-

acteristics (ΘJA), and the ambient temperature, as calculated with the following equation:

TJMAX = TAMAX + (Power * ΘJA)

The user must determine this temperature and then use it to determine the derating factor based on the following

derating tables: TJ °C.

Table 3-4. Delay Derating Table for Internal Blocks

TJ °C

Commercial

TJ °C

Industrial

Power Supply Voltage

1.14V

1.2V

1.26V

—

-40

0.82

0.77

0.71

—

-25

0.82

0.76

0.71

020

0.89

0.83

0.78

0.93

0.87

0.81

105

1.00

0.94

0.89

100

115

1.00

0.95

0.90

110

—

1.00

0.95

0.90

125

—

1.02

0.96

0.91

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