SSD1306Z datasheet(13/65 Pages) ETC2

13 / 65 page

SSD1306

Rev 1.1

P 13/59

Apr 2008

Solomon Systech

PIN DESCRIPTION

Key:

I = Input

NC = Not Connected

O =Output

Pull LOW= connect to Ground

I/O = Bi-directional (input/output) Pull HIGH= connect to VDD

P = Power pin

Figure 7-1 Pin Description

Pin Name

Type

Description

VDD

Power supply pin for core logic operation.

VCC

Power supply for panel driving voltage. This is also the most positive power voltage

supply pin.

VSS

This is a ground pin.

VLSS

This is an analog ground pin. It should be connected to VSS externally.

VCOMH

The pin for COM signal deselected voltage level.

A capacitor should be connected between this pin and VSS.

VBAT

Reserved pin. It should be connected to VDD.

BGGND

Reserved pin. It should be connected to ground.

C1P/C1N

C2P/C2N

Reserved pin. It should be kept NC.

VBREF

Reserved pin. It should be kept NC.

BS[2:0]

MCU bus interface selection pins. Please refer to Table 7-1 for the details of setting.

IREF

This is segment output current reference pin.

A resistor should be connected between this pin and VSS to maintain the IREF current at

12.5 uA. Please refer to Figure 8-15 for the details of resistor value.

This pin outputs RAM write synchronization signal. Proper timing between MCU data

writing and frame display timing can be achieved to prevent tearing effect.

It should be kept NC if it is not used. Please refer to Section 8.4 for details usage.

This is external clock input pin.

When internal clock is enabled (i.e. HIGH in CLS pin), this pin is not used and should be

connected to VSS. When internal clock is disabled (i.e. LOW in CLS pin), this pin is the

external clock source input pin.

CLS

This is internal clock enable pin. When it is pulled HIGH (i.e. connect to VDD), internal

clock is enabled. When it is pulled LOW, the internal clock is disabled; an external clock

source must be connected to the CL pin for normal operation.

RES#

This pin is reset signal input. When the pin is pulled LOW, initialization of the chip is

executed. Keep this pin HIGH (i.e. connect to VDD) during normal operation.

CS#

This pin is the chip select input. (active LOW).

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