TPS1663 datasheet(15/43 Pages) TI1

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D(INRUSH)

(IN)

(INRUSH)

0.5 V

VIN

VOUT

PGOOD

IIN

TPS1663

www.ti.com

SLVSET9D – SEPTEMBER 2018 – REVISED AUGUST 2019

Product Folder Links: TPS1663

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Feature Description (continued)

CdVdT = 100 nF

COUT = 1000 µF

RILIM = 4.02 kΩ

Figure 15. Hot Plug In and Inrush Current Control at 24-V Input

9.3.1.1 Thermal Regulation Loop

The average power dissipation within the eFuse during power up with a capacitive load can be calculated using

Equation 3.

(3)

System designs requiring to charge large output capacitors rapidly may result in an operating point that exceeds

the power dissipation versus time boundary limits of the device defined by Figure 13 characteristic curve. This

may result in increase in junction temperature beyond the device's maximum allowed junction temperature. To

keep the junction temperature within the operating range, the thermal regulation control loop regulates the

junction temperature at T(J_REG) , 145°C (typical) by controlling the inrush current profile and thereby limiting the

power dissipation within the device automatically. An internal 1.25 sec (typical), t(Treg_timeout) timer starts from the

instance the thermal regulation operation kicks in. If the output does not power up within this time then the

internal FET is turned OFF. Subsequent operation of the device depends on the MODE configuration (Auto-Retry

or latch OFF) setting as per the Table 1. The maximum time-out of 1.25 sec (typical) in thermal regulation loop

operation ensures that the device and the system board does not heat up during steady fault conditions such as

wake up with output short-circuit. This scheme ensures reliable power up operation.

Thermal regulation control loop is internally enabled during power up by V(IN), UVLO cycling and turn ON using

SHDN contol. Figure 16 illustrates performance of the device operating in thermal regulation loop during power

up by V(IN) with a large output capacitor. The Thermal regulation loop gets disabled internally after the power up

sequence when the internal FET's gate gets fully enhanced or when the t(Treg_timeout) of 1.25 sec (typical) time is

elapsed.

TPS1663 Datasheet(PDF) 15 Page - Texas Instruments