HM8563 datasheet(13/22 Pages) HMSEMI

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start-up times experienced by these types of circuits, a mechanism has been built in to disable

the POR and hence speed up on-board test of the device. The setting of this mode requires

that the I2C-bus pins, SDA and SCL, be toggled in a specific order as shown in Fig 5. All timing

values are required minimum.

Once the override mode has been entered, the chip immediately stops being reset and

normal operation starts i.e. entry into the EXT_CLK test mode via I2C-bus access. The

override mode is cleared by writing a logic 0 to bit TESTC. Re-entry into the override mode is

only possible after TESTC is set to logic 1. Setting TESTC to logic 0 during normal operation

has no effect except to prevent entry into the POR override mode.

Fig 5 POR override sequence.

3 Serial interface

The serial interface of

HM8563 is the I2C -bus, which requires minimum connections

between MPU and it peripherals ——.a serial Data I/O line and a serial CLK line driven by

MPU.

3.1 I2C Specification

The I2C -bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when

the bus is idle.

The I2C -bus system configuration is shown in Fig 6. A device generating a message is a

‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the

message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.

Fig 6 I2C-bus system configuration.

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH is defined as the start condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop

HM8563

HM8563 Datasheet(PDF) 13 Page - Shenzhen Huazhimei Semiconductor Co., Ltd