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HY27LF161G2M-VIP Datasheet(PDF) 21 Page - Hynix Semiconductor

No. de pieza HY27LF161G2M-VIP
Descripción Electrónicos  1Gbit (128Mx8bit / 64Mx16bit) NAND Flash Memory
PDF  48 Pages
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Fabricante Electrónico  HYNIX [Hynix Semiconductor]
Página de inicio  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

HY27LF161G2M-VIP Datasheet(HTML) 21 Page - Hynix Semiconductor

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Rev 0.7 / Apr. 2005
21
Preliminary
HY27UF(08/16)1G2M Series
HY27SF(08/16)1G2M Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Parameter
Symbol
1.8Volt
3.3Volt
Unit
Min
Max
Min
Max
CLE Setup time
tCLS
5(2)
5(2)
ns
CLE Hold time
tCLH
15(2)
15(2)
ns
CE# setup time
tCS
00
ns
CE# hold time
tCH
10
10
ns
WE# pulse width
tWP
40(2)
40(2)
ns
ALE setup time
tALS
5(2)
5(2)
ns
ALE hold time
tALH
15(2)
15(2)
ns
Data setup time
tDS
25(2)
25(2)
ns
Data hold time
tDH
15
15
ns
Write Cycle time
tWC
60(2)
60(2)
ns
WE# High hold time
tWH
20
20
ns
ALE to Data Loading time
tADL
100
100
ns
Data Transfer from Cell to register
tR
27(2)
27(2)
us
ALE to RE# Delay (ID Read)
tAR
10
10
ns
CLE to RE# Delay
tCLR
10
10
ns
Ready to RE# Low
tRR
20
20
ns
RE# Pulse Width
tRP
25(2)
25(2)
ns
WE# High to Busy
tWB
100
100
ns
Read Cycle Time
tRC
60(2)
60(2)
ns
RE# Access Time
tREA
30
30
ns
RE# High to Output High Z
tRHZ
30
30
ns
CE# High to Output High Z
tCHZ
20
20
ns
RE or CE High to Output hold
tOH
15
15
ns
RE# High Hold Time
tREH
30(2)
30(2)
ns
Output High Z to RE# low
tIR
00
ns
CE# Access Time
tCEA
45
45
ns
WE# High to RE# low
tWHR
60
60
ns
Device Resetting Time
(Read / Program / Erase)
tRST
5/10/500(1)
5/10/500(1)
us
Table 13: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. These parameters are applied to the errata.
3. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.



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