ESP32 datasheet(18/60 Pages) ESPRESSIF

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2. Pin Deﬁnitions

To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host

MCU’s GPIOs to control the voltage level of these pins when powering on ESP32.

After reset release, the strapping pins work as normal-function pins.

Refer to Table 3 for a detailed boot-mode configuration by strapping pins.

Table 3: Strapping Pins

Voltage of Internal LDO (VDD_SDIO)

Default

3.3 V

1.8 V

MTDI

Pull-down

Booting Mode

Default

SPI Boot

Download Boot

GPIO0

Pull-up

GPIO2

Pull-down

Don’t-care

Enabling/Disabling Debugging Log Print over U0TXD During Booting

Default

U0TXD Toggling

U0TXD Silent

MTDO

Pull-up

Timing of SDIO Slave

Default

Falling-edge Sampling

Falling-edge Output

Falling-edge Sampling

Rising-edge Output

Rising-edge Sampling

Falling-edge Output

Rising-edge Sampling

Rising-edge Output

MTDO

Pull-up

GPIO5

Pull-up

Note:

• Firmware can configure register bits to change the settings of ”Voltage of Internal LDO (VDD_SDIO)” and ”Timing

of SDIO Slave”, after booting.

• For ESP32 chips that contain an embedded flash, users need to note the logic level of MTDI. For example, ESP32-

D2WD contains an embedded flash that operates at 1.8 V, therefore, the MTDI should be pulled high.

The illustration below shows the setup and hold times for the strapping pin before and after the CHIP_PU signal

goes high. Details about the parameters are listed in Table 4.

CHIP_PU

Strapping pin

IL_nRST

Figure 6: Setup and Hold Times for the Strapping Pin

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