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GPCL020B1 Datasheet(PDF) 8 Page - Generalplus Technology Inc.

No. de pieza GPCL020B1
Descripción Electrónicos  Low Power Sound Conttrollller Seriies
PDF  19 Pages
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Fabricante Electrónico  GENERALPLUS [Generalplus Technology Inc.]
Página de inicio  http://www.generalplus.com
Logo GENERALPLUS - Generalplus Technology Inc.

GPCL020B1 Datasheet(HTML) 8 Page - Generalplus Technology Inc.

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GPCL A1/B1 Series
© Generalplus Technology Inc.
Proprietary & Confidential
8
Sep. 15, 2015
Version: 1.0
7.6. IO Port Configuration
Register
Control
logic
Pin pad
Buffer(R)
Data(R)
Port_Data(W)
Port_Buffer(W)
Port_DIR(R/W)
Input/Output IOC port : IOC3 - IOC0
Register
Control
logic
pull low
Pin pad
Buffer(R)
Data(R)
Port_Data(W)
Port_Buffer(W)
Port_DIR(R/W)
Input/Output IOD port : IOD7 - IOD0
7.7. DC-DC
GPCL A1/B1 series can work wide input voltage (1.0V~1.7V;
1.3V~3.6V).
Inside the chip, it is implemented a high efficient
DC-DC circuit.
The DC-DC circuit pumps input voltage to
programmed voltage that supplies chip as working voltage.
7.8. Power Saving Mode
The GPCL A1/B1 series includes a power saving mode (Standby
mode) for those applications that require very low standby current.
To enter standby mode, the Wake-up Register must be enabled
and then stop the CPU clock by writing the STOP CLOCK
Register to enter standby mode.
In such mode, RAM and I/Os
will retain at the previous states until awakened.
Port IOD7-0 is
the only wake-up source in the GPCL A1/B1 series.
After GPCL
A1/B1 series wakes up, the internal CPU will stay at RESET state
for a period (Tw) and then continue to execute program.
Wakeup
Reset will neither affect RAM, nor I/Os.
T1
Tw
Wake-up
CPU CLK
SLEEP
RESET
T1 = 1 / ( FCPU )
7.9. Timer/Counter
The GPCL A1/B1 series has two 8-bit timer/counters, TMA and
TMB respectively.
TMA can be specified as a timer, but TMB can
be used as a timer or a counter.
In the timer mode, TMA and
TMB are re-loaded up-counters.
When timer rolls over from $FF
to $00,
the carry (overflow) signal will make the user’s preset
value to be loaded into timer automatically and count up again.
At the same time, the carry signal will generate an INT signal if the
corresponding bit is enabled in the INT ENABLE Register.
Suppose TMB is specified as a counter, it can be reset by loading
#00 into the counter.
After the counter has been activated, the
value in the counter can also be read at the same time.
The read
instruction will neither affect the value of the counter nor reset it.
Clock source of Timer/Counter can be selected as follows:
Timer/Counter
Clock Source
TMA
8-BIT TIMER
CPU CLOCK (T) or T/8, T/64, TMB overflow
TMB
8-BIT TIMER
T, T/65536, EXTCLK, 0, 1



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