MSM82C59A-2JS datasheet(5/28 Pages) OKI

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¡ Semiconductor

MSM82C59A-2RS/GS/JS

AC CHARACTERISTICS

AC Test Circuits

Test Point

C1*

Output from

Device under Test

* Includes Stray and Jig Capacitance

1.7 V 523 W Open

Test Condition

4.5 V 1.8k W 1.8k W

100 pF

30 pF

Test Condition Definition Table

VIH+0.4 V

Input

Output

VIL–0.4 V

1.5V

1.5 V

VOH

VOL

A. C. Testing: All input signals must switch between

VIL–0.4 V and VIH+0.4 V.

TR and TF must be less than of equal to 15 ns.

A.C. Testing Input, Output Waveform

Min.

Max.

Address Setup Time (to RD)

tAHRL

—ns

Address Hold Time (after RD)

tRHAX

—ns

Parameter

Unit

Symbol

TEST Conditions

RD/INTA Pulse Width

tRLRH

160

—ns

Address Setup Time (to WR)

tAHWL

—ns

WR Pulse Width

tWLWH

190

—ns

Data Setup Time (to WR)

tDVWH

160

—ns

Data Hold Time (after WR)

tWHDX

—ns

IR Input Width(Low)

tJLJH

100

—ns

tCVIAL

—ns

tRHRL

160

—ns

End of RD to Next RD

End of INTA to Next INTA

End of WR to Next WR

tWHWL

190

—ns

End of Command to Next Command

tCHCL

400

—ns

Data Valid Following RD/ INTA

tRLDV

—

120

Data Floating Following RD/ INTA

tRHDZ

INT Output Delay Time

tJHIH

—

300

CAS Valid Following 1 st. INTA (master)

tIALCV

—

360

EN Active Following RD/INTA

tRLEL

—

100

EN Inactive Following RD/ INTA

tRHEH

—

150

Data Valid after Address

tAHDV

—

200

Data Valid after CAS

tCVDV

—

200

Ta = –40°C - +85°C, VCC = 5 V ± 10%

Address Hold Time (after WR)

tWHAX

0—

CAS Input Setup Time (to INTA) (Slave)

Read INTA timing

Write timing

INTA sequence

Other timing

Delay times

—

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