MPC7445 datasheet(27/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 13 provides the L3 bus interface AC timing specifications for the configuration shown in Figure 11, assuming

the timing relationships of Figure 12 and the loading of Figure 8.

Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades 6

Unit Notes

L3OH0 = 0, L3OH1 = 0 L3OH0 = 0, L3OH1 =1 L3OH0 = 1, L3OH1 = 0 L3OH0 = 1, L3OH1 = 1

Min

Max

Min

Max

Min

Max

Min

Max

L3_CLK rise

and fall time

tL3CR,

tL3CF

—

1.0

—

1.0

—

1.0

—

1.0

1, 5

Setup times:

Data and

parity

tL3DVEH

1.5

—

1.5

—

1.5

—

1.5

—

2, 5

Input hold

times: Data

and parity

tL3DXEH

—

0.5

—

0.5

—

0.5

—

0.5

2, 5

Valid times:

Data and

parity

tL3CHDV

—tL3_CLK/4

+ 1.00

—tL3_CLK/4

+ 0.80

—tL3_CLK/4

+ 0.60

—tL3_CLK/4

+ 0.40

3, 4, 5

Valid times: All

other outputs

tL3CHOV

—tL3_CLK/4

+ 1.00

—tL3_CLK/4

+ 0.80

—tL3_CLK/4

+ 0.60

—tL3_CLK/4

+ 0.40

Output hold

times: Data

and parity

tL3CHDX tL3_CLK/4

– 0.40

—tL3_CLK/4

– 0.60

—tL3_CLK/4

– 0.80

—tL3_CLK/4

– 1.00

—

3, 4, 5

Output hold

times: All other

outputs

tL3CHOX tL3_CLK/4

– 0.40

—tL3_CLK/4

– 0.60

—tL3_CLK/4

– 0.80

—tL3_CLK/4

– 1.00

—ns

4, 5

L3_CLK to

high

impedance:

Data and

parity

tL3CHDZ

—

2.0

—

2.0

—

2.0

—

2.0

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