PIC12F635ESLASHP datasheet(98/196 Pages) MICROCHIP

98 / 196 page

PIC12F635/PIC16F636/639

DS41232B-page 96

Preliminary

11.31.2

CARRIER CLOCK OUTPUT

When the Carrier Clock output is selected, the LFDATA

output is a square pulse of the input carrier clock and

available as soon as the AGC stabilization time (TAGC) is

completed. There are two Configuration register options

for the carrier clock output: (a) clock divide-by one or (b)

clock divide-by four, depending on bit DATOUT<7> of

Configuration Register 2 (Register 11-3). The carrier

clock output is available immediately after the AGC

settling time. The Output Enable Filter, AGCSIG, and

MODMIN options are applicable for the carrier clock

output in the same way as the demodulated output. The

input channel can be individually enabled or disabled for

the output. If more than one channel is enabled, the

output is the sum of each output of all enabled channels.

Therefore, the carrier clock output waveform is not as

precise as when only one channel is enabled. It is

recommended to enable one channel only if a precise

output waveform is desired.

There will be no valid output if all three channels are

disabled. See Figure 11-13 for carrier clock output

examples.

Related Configuration register bits:

• Configuration Register 1 (Register 11-2),

DATOUT <8:7>:

bit 8 bit 7

: Demodulator Output

: Carrier Clock Output

: RSSI Output

• Configuration Register 2 (Register 11-3),

CLKDIV<7>:

: Carrier Clock/1

: Carrier Clock/4

• Configuration Register 0 (Register 11-1): all bits

are affected

• Configuration Register 5 (Register 11-6)

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