CS42406 datasheet(32/50 Pages) CIRRUS

32 / 50 page

CS42406

DS614PP5

4.2.2

Operation as a Clock Slave

ADC_LRCK and ADC_SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be

synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock

be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance. Please

refer to Table 1 and Table 2 for supported SCLK ratios.

A unique feature of the CS42406 ADC serial port is the automatic selection of either Single, Double or Quad-Speed

Mode when operating as a clock slave. The auto-mode selection feature supports all standard audio sample rates

from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when op-

erating with a fast MCLK (512x/768x, 256x/384x, 128x/192x for Single, Double, and Quad-Speed Modes, respec-

tively). Please refer to Table 1 and Table 2 for supported sample rate ranges.

4.3

Digital Interface Format

4.3.1

DAC Serial Port

The CS42406 DAC serial port will accept audio samples in 1 of 4 digital interface formats in Stand Alone

Mode (as illustrated in Table 6), and 1 of 6 formats in Control Port mode (as illustrated in Table 7 on page

41).

÷ 128

÷ 256

÷ 64

ADC_M0

ADC_M1

ADC_LRCK

Output

(Equal to Fs

out)

Single

Speed

Quad

Speed

Double

Speed

÷ 2

÷ 4

÷ 1

ADC_SCLK

Output

Single

Speed

Quad

Speed

Double

Speed

÷ 1.5

÷ 1

MCLK

Auto-Select

÷ 2

÷ 3

Auto-Select

ADC_384x/256x

Figure 34. ADC Serial Port, Master Mode Clocking

CS42406 Datasheet(PDF) 32 Page - Cirrus Logic

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