CS5466

6

Notes:

2.

All outputs unloaded. All inputs CMOS level.

3.

Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV zero-to-peak sine wave (frequency =

60 Hz) is imposed onto the +5 V supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input

channels are shorted to VA-. Then the CS5466 is put into an internal test mode and digital output data is collected

for the channel under test. The zero-peak value of the digital sinusoidal output signal is determined, and this value

is converted into the zero-peak value of the sinusoidal voltage that would need to be applied at the channel’s inputs,

in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):

VOLTAGE REFERENCE

Notes:

4.

The voltage at VREFOUT is measured across the temperature range. From these measurements the following

formula is used to calculate the VREFOUT Temperature Coefficient

:.

5.

Specified at maximum recommended output current of 1

µA, source or sink.

Parameter

Symbol

Min

Typ

Max

Unit

Power Supplies

Power Supply Currents

PSCA

PSCD

PSCD

-

-

-

1.3

2.9

1.7

-

-

-

mA

mA

mA

Power Consumption

(VA+ = VD+ = 5 V)

(Note 2)

(VA+ = 5 V, VD+ = 3.3 V)

PC

-

-

21

11.6

25

-

mW

mW

Power Supply Rejection Ratio

(50, 60 Hz)

(Note 3)

Voltage Channel (Gain = 10)

Current Channel (Gain = 10)

(Gain = 50)

(Gain = 100)

(Gain = 150)

PSRR

45

75

56

56

56

-

55

-

75

75

75

-

-

-

-

-

-

dB

dB

dB

dB

dB

PSRR

20

0.150V

V

eq

------------------

⎩⎭

⎨⎬

⎧⎫

log

⋅

=

Parameter

Symbol

Min

Typ

Max

Unit

Reference Output

Output Voltage

REFOUT

+2.4

+2.5

+2.6

V

VREFOUT Temperature Coefficient

(Note 4)

25

60

ppm/°C

Load Regulation

(Note 5)

610

mV

Reference Input

Input Voltage Range

VREFIN

+2.4

+2.5

+2.6

V

Input Capacitance

-

4

-

pF

Input CVF Current

-

25

-

nA

(

1

T

A

MAX

- T

A

MIN

(

1.0 x 10

(

6

TC