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AR8327-AL1A-R Datasheet(PDF) 134 Page - List of Unclassifed Manufacturers

No. de pieza AR8327-AL1A-R
Descripción Electrónicos  Seven-port Gigabit Ethernet Switch
PDF  394 Pages
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Fabricante Electrónico  ETC2 [List of Unclassifed Manufacturers]
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AR8327-AL1A-R Datasheet(HTML) 134 Page - List of Unclassifed Manufacturers

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134 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch
Atheros Communications, Inc.
134 • June 2011
COMPANY CONFIDENTIAL
SFT&HW RST
Table 3-116 summarizes the GOL_LEARN_LIMIT Register
Table 3-116.
Global Learn Limit Control Register
3.6.11
TOS_PRI_MAP_REG0
Address 0x0630
SFT&HW RST
Table 3-117 summarizes the TOS_PRI_MAP_REG0 Register 0
Table 3-117.
TOS Priority Mapping Register Register 0
Bit
R/W
Inital
Value
Mnemonic
Description
31:13
R/O
0
RESERVED
12
R/W
0
GOL_SA_LEARN_LIMIT_EN
1'b1: SA Learn Limit enable.
11
R/W
0
GOL_SA_LEARN_LIMIT_DROP_
EN
1'b1: if SA is not in ARL table or SA in
ARL but port member is not the source
port, packet should be dropped when
Learned MAC address counter is equal
to GOL_SA_LEARN_CNT
1'b0: if SA is not in ARL table or SA in
ARL but port member is not the source
port, packet should be redirect to cpu
when Learned MAC address counter
is equal to GOL_SA_LEARN_CNT
10:0
R/W
0
GOL_SA_LEARN_CNT
The MAC address can be learned and
written to the ARL table — only
dynamic entry is counted
0: indicates no MAC limit number is 1
1: indicates the MAC limit number is 2
2: indicates the MAC limit number is 3
... and so on ... until:
2047: indicates the MAC limit is 2048
Bit
R/W
Inital
Value
Mnemonic
Description
31:28
R/W
0
TOS_MAP_0X1C
See bit 3:0
27:24
R/W
0
TOS_MAP_0X18
See bit 3:0
23:20
R/W
0
TOS_MAP_0X14
See bit 3:0
19:16
R/W
0
TOS_MAP_0X10
See bit 3:0
15:12
R/W
0
TOS_MAP_0X0C
See bit 3:0
11:8
R/W
0
TOS_MAP_0X08
See bit 3:0



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