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CS42526 Datasheet(PDF) 79 Page - Cirrus Logic

No. de pieza CS42526
Descripción Electrónicos  114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
PDF  90 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42526 Datasheet(HTML) 79 Page - Cirrus Logic

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CS42526
12. APPENDIX C: PLL FILTER
The PLL has been designed to only use the preambles of the S/PDIF stream to provide lock update infor-
mation to the PLL. This results in the PLL being immune to data dependent jitter effects because the
S/PDIF preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component chang-
es. The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an
S/PDIF data stream.
Phase
Com parator
and Charge Pum p
÷N
VCO
RM CK
INPUT
CRIP
CFILT
RFILT
Figure 27. PLL Block Diagram



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