AP72200

I

2

C – Compatible Interface Timing (Standard, Fast, and Fast Mode Plus) (Note 8)

Clock Frequency

—

—

—

—

MHz

Setup Time (Repeated) Start

Condition

SCL rising edge to SDA falling

edge; Both crossing High

threshold

0.26

—

—

μs

Hold Time (Repeated) Start

Condition

From SDA falling edge

crossing Low threshold to SCL

falling edge crossing High

threshold

0.26

—

—

μs

SCL low period

Time measured during the

Low voltage threshold

0.5

—

—

μs

SCL high period

Time measured during the

High voltage threshold

0.26

—

—

μs

Input Data Hold Time

From SCL falling edge

crossing Low threshold to

SDA entering the Low-High

window

0

—

—

μs

Input Data Setup Time

From SDA exiting the Low-

High window to SCL rising

edge crossing Low threshold

50

—

—

ns

Setup Time for Stop Condition

From SCL rising edge

crossing High threshold to

SDA rising edge crossing Low

threshold

0.26

—

—

μs

Bus-Free Time Between Stop and

Start

From SDA crossing High

threshold during STOP

condition to SDA crossing

High threshold for the

following START condition

0.5

—

—

μs

Maximum Pulse width of Spike That

Must be Suppressed by the Input

Filter

Any pulse width narrower than

the maximum specification is

suppressed

—

50

—

ns

Capacitive Load for each Bus Line

Total on-chip and off-chip

capacitance

—

—

550

pF

Note:

8. All minimum and maximum parameters compliance to the datasheet limits are assured by one or more methods: production test, characterization, and/or

design.

AP72200

Document number: DS40869 Rev. 3 - 2

7 of 30

www.diodes.com

July 2018

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