 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
AM652X Datasheet(PDF) 117 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
AM652X Datasheet(HTML) 117 Page - Texas Instruments |
|
|
117 / 299 page  117 AM6548, AM6528, AM6546 AM6526, AM6527 www.ti.com SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2018, Texas Instruments Incorporated Absolute Maximum Ratings (continued) over operating free-air temperature range (unless otherwise noted) (1)(2)(3) PARAMETERS MIN MAX UNIT VDDS5 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS6 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS7 Supply voltage range for dual-voltage IO domain TBD TBD V VDDS8 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV0 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV0_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV1 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV1_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV2 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV2_WKUP Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV3 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV4 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV5 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV6 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV7 Supply voltage range for dual-voltage IO domain TBD TBD V VDDSHV8 Supply voltage range for dual-voltage IO domain TBD TBD V VPP_CORE Supply voltage range for CORE EFUSE domain TBD TBD V VPP_MCU Supply voltage range for MCU EFUSE domain TBD TBD V USB0_VBUS Voltage range for USB VBUS comparator input TBD TBD V USB1_VBUS Voltage range for USB VBUS comparator input TBD TBD V Steady State Max. Voltage at all IO pins (4) TBD V Transient Overshoot and Undershoot specification at IO terminal (5) TBD V Latch-up Performance (6) Class II (105°C) Latch-up I-test performance current-pulse injection on each IO pin TBD TBD mA Latch-up overvoltage performance voltage injection on each IO pin TBD TBD mA TSTG Storage temperature after soldered onto PC board TBD TBD °C Latch-up I-test I-test, all I/Os (if different levels, then one line per level) TBD TBD mA Latch-up OV-test Overvoltage test, all supplies (if different levels, then one line per level) N/A TBD V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4, Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted. (3) To determine which power supply is associated with any IO refer to Table 4-1, Pin Attributes. (4) This parameter applies to all IO terminals which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –TBD to +IO supply + TBD volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences. (5) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8 V LVCMOS signals is VDDS18V6/9 + (0.20 × VDDS18V6/9) and maximum undershoot value would be VSS - (0.20 × VDDS18V6/9). (6) For current pulse injection: Pins stressed per JEDEC JESD78D (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage. For overvoltage performance: Supplies stressed per JEDEC JESD78D (Class II) and passed specified voltage injection. Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, and NMIn are the only fail-safe IO terminals. All other IO terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in Section 5.1. |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
