ACE809N datasheet(5/8 Pages) ACE

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ACE803N/ACE809N/ACE810N

Ultra Low Power Microprocessor Reset IC

VER 1.2

Detailed Description

A microprocessor’s (μP’s) reset input starts the μP in a known state. The ACE803N/809N/810N series

assert reset to prevent code-execution errors during power-up, power-down, or brownout conditions. The

device consists of a comparator, a low current high precision voltage reference, voltage divider, output

delay circuit and output driver. They assert a reset signal whenever the VCC supply voltage declines below

a preset threshold, keeping it asserted for at least 140ms after VCC has risen above the reset threshold.

The ACE809N/810N have a CMOS output stage, the ACE803N has an open drain output stage. The

ACE803N/809N have an active-low RESET output, while the ACE810N has an active-high RESET output.

The reset comparator is designed to ignore fast transients on VCC, and the outputs are guaranteed to be in

the correct logic state for VCC down to 1.15V over the temperature range.

The operation of the device can be best understood by referring to figure 3.

Fig. 2 Timing waveform

Applications Information

Negative-Going VCC Transients

In addition to issuing a reset to the

μP during power-up, power-down, and brownout conditions, the

ACE803N/809N/810N series are relatively immune to short-duration negative-going VCC transients

(glitches). As the magnitude of the transient increases (goes farther below the reset threshold), the

maximum allowable pulse width decreases. Typically, a VCC transient that goes 100mV below the reset

threshold and lasts 10μs or less will not cause a reset pulse. A 0.1μF bypass capacitor mounted as close

as possible to the VCC pin provides additional transient immunity.

ACE809N Datasheet(PDF) 5 Page - ACE Technology Co., LTD.