AD9543BCPZ datasheet(14/66 Pages) AD

No. de pieza	AD9543BCPZ

Descripción Electrónicos	Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner

PDF	66 Pages

Scroll/Zoom	100%

Fabricante Electrónico	AD [Analog Devices]

Página de inicio	http://www.analog.com

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14 / 66 page

AD9543

Data Sheet

Rev. 0 | Page 14 of 66

SERIAL PORT SPECIFICATIONS

Serial Port Interface (SPI) Mode

Table 18.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CSB

Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V

Input Logic 1 Voltage

VDDIOA − 0.4

Input Logic 0 Voltage

0.4

Input Logic 1 Current

µA

Input Logic 0 Current

µA

SCLK

Input Logic 1 Voltage

VDDIOA − 0.4

Input Logic 0 Voltage

0.4

Input Logic 1 Current

µA

Input Logic 0 Current

µA

SDIO

As an Input

Input Logic 1 Voltage

VDDIOA − 0.4

Input Logic 0 Voltage

0.4

Input Logic 1 Current

µA

Input Logic 0 Current

µA

As an Output

Output Logic 1 Voltage

VDDIOA − 0.2

1 mA load current

Output Logic 0 Voltage

0.2

1 mA load current

SDO

Output Logic 1 Voltage

VDDIOA − 0.2

1 mA load current

Output Logic 0 Voltage

0.2

1 mA load current

Leakage Current

±1

µA

SDO inactive (high impedance)

TIMING

Valid for VDDIOA = 3.3 V, 1.8 V, and 2.5 V

SCLK

Clock Rate, 1/tCLK

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

2.2

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CSB to SCLK Setup, tS

1.5

CSB to SCLK Hold, tC

CSB Minimum Pulse Width High

tCLK

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