REVISION 10 3/18/15

6

LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP

MPC941 DATA SHEET

APPLICATIONS INFORMATION

Driving Transmission Lines

The MPC941 clock driver was designed to drive high-

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user, the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 20

 the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

AN1091 in the Timing Solutions data book (DL207/D).

In most high performance clock networks, point-to-point

distribution of signals is the method of choice. In a point-to-

point scheme, either series terminated or parallel terminated

transmission lines can be used. The parallel technique

terminates the signal at the end of the line with a 50



of DC current, and thus, only a single terminated line can be

driven by each output of the MPC941 clock driver. For the

series terminated case, however, there is no DC current

draw; thus, the outputs can drive multiple series terminated

lines. Figure 1 illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme, the fanout of the MPC941 clock

driver is effectively doubled due to its capability to drive

multiple lines.

Figure 1. Single versus Dual Transmission Lines

The waveform plots of Figure 2 show the simulation

results of an output driving a single line vs two lines. In both

cases, the drive capability of the MPC941 output buffer is

more than sufficient to drive 50

 transmission lines on the

incident edge. Note from the delay measurements in the

simulations, a delta of only 43 ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output-to-output skew of the MPC941. The output waveform

by the impedance mismatch seen looking into the driver. The

parallel combination of the 36

 series resistor plus the

output impedance does not match the parallel combination of

the line impedances. The voltage wave launched down the

two lines will equal:

= 1.31 V

At the load end, the voltage will double, due to the near

unity reflection coefficient, to 2.5 V. It will then increment

towards the quiescent 3.0 V in steps separated by one round

trip delay (in this case, 4.0 ns).

Figure 2. Single versus Dual Waveforms

Since this step is well above the threshold region, it will not

cause any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines, the

situation in Figure 3 should be used. In this case, the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance, the line

impedance is perfectly matched.

Figure 3. Optimized Dual Line Termination

MPC941

Output

Buffer

IN

14



OutA

OutB0

OutB1

MPC941

Output

Buffer

IN

14



3.0

2.5

2.0

1.5

1.0

0.5

0

24

68

10

12

14

TIME (ns)

OutB

OutA

IN

14

 + 22 || 22 = 50 ||50

25

 = 25

MPC941

Output

Buffer

14

